1. Field of the Invention
The present invention pertains to frequency locked loops, and particularly to calibrating loop bandwidth for a frequency locked loop.
2. Related Art and Other Considerations
Digital communications is an example of a technology which requires high quality reference signals. For example, a reference signal such as a timing or clock signal, generated externally to a node of a digital communications network (e.g., a node of a telecommunications network), can be applied over a transport network to the node. At the node the reference signal is extracted and used as a reference source or reference signal for the node.
Traditionally a frequency locked loop, functioning as a narrow bandwidth low pass filter, has been used to extract the reference signal for a digital communications node. Often the frequency locked loop has a primarily digital implementation. Two important parameters of a frequency locked loop are settling time and attenuation of jitter and wander. Both jitter and wander are undesired frequency modulation in the reference signal, jitter typically being above 10 Hz and wander usually being below 10 Hz. Such undesired modulation can be caused by various phenomena, such as cross-talk and temperature changes, for example.
In a frequency locked loop, a short settling time is usually desired, which typically involves a wide loop bandwidth. On the other hand, there is the competing demand to attenuate jitter and wander, which attenuation requires a low modulation bandwidth. The tension between shortening settling time and attenuating jitter and wander generally leads to a compromise for modulation bandwidth. The compromise often introduces substantial margins for which allowances must regrettably be made.
It is known to calibrate signal generators, such as the model HP8645 signal generator and the model HP8656 signal generator manufactured by Hewlett-Packard.
The model HP8645 signal generator has calibration to provide an updated tuning voltage table (voltage vs. frequency) for the purpose of making frequency hopping applications. Calibration for the model HP8656 signal generator involves measuring and using a relationship between tuning voltage and frequency for obtaining a constant deviation when frequency modulation is used.
What is needed, therefore, and an object of the present invention, is a calibration procedure and calibration system for calibrating loop bandwidth of a frequency locked loop to optimize both settling time and modulation bandwidth
A node of a communications network extracts a reference signal from a transport network for use as a reference signal for the node. The node comprises a frequency locked loop which filters the reference signal, as well as a calibration system which determines a tuning sensitivity factor for the frequency locked loop.
The frequency locked loop comprises a voltage controlled oscillator which generates an oscillator signal; a frequency detector which receives the reference signal and the oscillator signal; a processor which calculates a tuning correction signal; and, a digital to analog converter which converts the tuning correction signal to an analog tuning voltage for input to the voltage controlled oscillator.
The calibration system performs a calibration procedure which includes the calibration steps of (1) obtaining a first error measurement when a first voltage signal is utilized by the frequency locked loop; (2) obtaining a second error measurement when a second voltage signal is utilized by the frequency locked loop; and, (3) using the first error measurement and the second error measurement to determine a tuning sensitivity factor for the frequency locked loop.
In particular, a first tuning input data value (D1) is applied to the digital to analog converter to yield the first voltage signal value (V1); a second tuning input data value (D2) is applied to the digital to analog converter to yield the second voltage signal value (V2); the first error measurement is a first frequency error measurement (f1), and the second error measurement is a second frequency error measurement (f2). Determining the tuning sensitivity factor for the frequency locked loop involves determining a tuning slope by dividing a difference of the first frequency error measurement (f1) and the second frequency error measurement (f2) by a difference of the first tuning input data value (D1) and the second tuning input data value (D2).
In one embodiment, a filter circuit first receives the external reference signal and is connected to have its output signal (the filtered reference signal) applied to the frequency locked loop. The pre-filtering circuit aids in minimizing jitter and wander. Preferably the filter circuit is a phase locked loop, while the frequency locked loop is primarily digital in nature. In the calibration procedure, the extracted reference signal is disconnected from (not applied to) a phase detector of the filter circuit, and an oscillator of the filter circuit receives a stable tuning voltage so that the filter circuit outputs a stable and clean frequency reference signal to the frequency detector of the frequency locked loop.
In an example deployment, the communications node is a base station node of a cellular telecommunications system, such as a wide band code division multiple access (CDMA) network wherein the reference signal is applied to the base station node over an Asynchronous Transfer Mode (ATM) transport network.